The disclosed invention relates in general to circuit testing and more particularly to in-circuit testing utilizing data compression techniques to reduce equipment costs, speed-up test rates and reduce problems due to overheating of elements in the circuits under test. In early generations of circuit testers, circuits were tested by a method, known as functional testing, in which test signals are applied only at circuit inputs and output signals are monitored only at circuit outputs. Such functional testing suffers from at least two serious limitations. First, it is difficult to determine test patterns suitable for testing the circuit under test since each circuit is unique. Second, isolation of a fault requires backtracing of the circuit and does not lend itself to automatic diagnosis.
These limitations are particularly severe in circuits containing some sort of sequential circuits (e.g. RAM, flip-flops, etc.) because the output of the circuit is a function of the state of the circuit as well as of the applied test signals. In order to know the state of a circuit with sequential elements, it is generally necessary to apply to the inputs of its sequential elements a set of signals which alter that element's state until it enters a desired state known as its home state. The application of these signals is known as homing. Because of the complicated relation in functional testing between the signals applied at the circuit inputs and the resulting signals produced at the inputs of the individual circuit components, it is extremely difficult to determine the signals which must be applied at the circuit inputs to home the circuit. As a result of the limitations of functional testing, many circuit testers utilize a technique known as in-circuit testing in which individual components are tested directly by in-circuit application of test signals directly to the inputs of each component and observing at the outputs of each component the resulting output signals.
The use of in-circuit testing has greatly increased the thoroughness with which a circuit can be tested, but unfortunately has also introduced some problems. The back-driving of circuit nodes (i.e. the imposition of a test signal which overrides the voltage applied to that node by circuit components connected to that node) results in the heating of circuit components which can be damaged if the duration of the test is too long (on the order of hundreds of milliseconds). The number of test signals required for a complete in-circuit test is much greater than that required in functional testing. This number is also increasing dramatically as circuit complexity and speed increases. The amoung of test information tht must be stored in the tester to test many types of circuits has become great enough that there is a real need to compress the amount of test information that needs to be stored to minimize possible damage from overheating, to reduce tester memory requirements and to increase tester throughput.
In the Zehntel Troubleshooter 800 circuit tester, a Gray code counter is used to apply test signals to input test pins. Each of the input test pins is connected to one of the bits of this counter. The counter is the major source of stimulus to a circuit under test. The output from each of the output pins is compressed by a serial cyclic redundancy check (CRC) compression technique to produce for each pin a compressed piece of output data known as a signature. In a test system having a single serial CRC compressor, a device with N outputs requires N repetitions of stimulus and response detection. These signatures are compared with the signatures produced by a known good circuit to check for circuit malfunctions. Such a system is much less suitable for generating the predetermined random set of signals needed to test circuits at least as complex as typical medium scale integration circuits than it is for generating the set of signals to test circuits that can be tested algorithmically, such as ROMs and RAMs. Because of the random nature of the input test signals, this system is not well adapted to homing circuit components.
In another class of circuit testers such as the model 2270 circuit tester manufactured by GenRad, Inc., each node in the circuit under test is connected to a pin on which test signals are applied or output signals are monitored. Each pin can be used in different test cycles to apply test signals or supply an expected response signal to be compared with an output signal monitored at that pin. In order to test circuits at high speed, each pin is connected to an associated RAM in which is stored the stimulus and response (S/R) data for that pin. This enables the S/R data to be applied in short bursts. Unfortunately, a typical RAM associated with a pin has only on the order of 1K bits so that many circuits require a large amount of data to be downloaded to these S/R data RAMs from a larger memory such as disc memory. This large amount of downloaded data requires many reloads of each of these RAMs to execute a complete test of the circuit. For example, a 64K RAM requires on the order of 250 reloads for a complete test. The time required for such reloads significantly increases the duration of many tests, thereby reducing tester throughput and increasing the risk of damage to the circuit under test.